A gate spacer is formed around edges of a gate electrode that is located over a channel area of a field effect transistor. The gate spacer comprises a dielectric material to prevent an electrical short between the gate electrode and source and drain regions. The gate spacer allows formation of a self-aligned silicide (salicide) without electrically bridging the gate conductor and the source and drain regions. The gate spacer is also used to control the proximity of the source and drain regions to the edges of the gate electrode.
Silicon nitride and silicon oxide are typically employed as the gate spacer for the practical reason that these materials may be etched selective to silicon. Further, silicon oxide and silicon nitride may also be etched selective to each other by a wet etch or a reactive ion etch (RIE). Use of a plurality of spacers employing silicon nitride and silicon oxide is also known in the art. One of the drawbacks of conventional gate spacers employing silicon nitride and/or silicon oxide is the formation of a parasitic capacitor between the gate electrode and contacts to the source and drain regions. Specifically, the gate electrode functions as one electrode of the parasitic capacitor, the contacts to the source and drain regions function as another electrode of the parasitic capacitor, and the gate spacer functions as the capacitor dielectric. The dielectric constants of silicon nitride and silicon oxide are 7.5 and 3.9, respectively, which provide a relatively high parasitic capacitance between the gate electrode and the source and drain regions.
While use of silicon oxide provides reduced parasitic capacitance between a gate electrode and contacts to the source and drain regions relative to silicon nitride due to a lower dielectric constant of silicon oxide than that of silicon nitride, use of silicon oxide allows diffusion of oxygen to a gate dielectric. Such diffusion of oxygen through a silicon oxide gate spacer induces changes in composition in a high-k gate dielectric material, which results in a shift in a threshold voltage (Vt) as a result of the compositional change of the high-k gate dielectric material.
Thus, silicon nitride employed as a gate spacer induces a high parasitic capacitance, while silicon oxide employed as a gate spacer provides a path for diffusion of oxygen to the gate dielectric and subsequent shift in the threshold voltage of the field effect transistor.
In view of the above, there exists a need for methods of forming a field effect transistor having a reduced parasitic capacitance, while preventing diffusion of oxygen to a high-k gate dielectric.